Sydney Hauke

A note on using the FPGA-to-SDRAM bus

On Alter-Intel SoCs, there exist a bus connecting directly the FPGA fabric and the SDRAM called FPGA-to-SDRAM. This bus is not shared with any other peripheral and enables high-throughput data transfers between the FPGA and the SDRAM. Typically, you might want to use it for DMA transfers. By default, this bus might not be enabled and prevents anyone from attempting a single transfer on it. If your FPGA design interfaces with this bus, you might need to enable the bus’…

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Using the mSGDMA IP : an introduction

Hardware accelerated computations is a rising trend today. More and more, we are moving towards heterogeneous systems where a CPU and one or more hardware accelerators collaborate together to speedup computationally intensive tasks. FPGAs, with their reconfiguration capabilities, are very good candidates towards hardware acceleration. One very important part in this field is data transfers between a CPU and a hardware accelerator, as they are a critical in such a high performance environment. On FPGAs, though, how does data transfer…

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About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at http://www.reds.ch