Using the mSGDMA IP : an introduction

Hardware accelerated computations is a rising trend today. More and more, we are moving towards heterogeneous systems where a CPU and one or more hardware accelerators collaborate together to speedup computationally intensive tasks. FPGAs, with their reconfiguration capabilities, are very good candidates towards hardware acceleration. One very important part in this field is data transfers between a CPU and a hardware accelerator, as they are a critical in such a high performance environment. On FPGAs, though, how does data transfer…

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Link with the parallel version of libstdc++ and take advantage of your multi-core processor “for free”

Going from a single threaded program to a parallel version is often a major pain, this is however often needed to take full advantage of modern multi-core processors. Having to work with threads, locks, and shared data structures is often difficult due to the non deterministic behavior of the scheduler and the difficulty in debugging the complex problems that can happen with multi-threading. It should be noted that several algorithms in the C++ library already have a parallel implementation. If…

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About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at http://www.reds.ch