La reconfiguration partielle sur FPGA pour des applications dans les appareils de radio définie par logiciel (SDR)

L’une des spécialités de l’institut REDS est le développement de systèmes reconfigurables à haute performance, et l’une de ses activités principales est la radio définie par logiciel – Software Defined Radio (SDR). La faisabilité de la reconfiguration partielle sur des circuits FPGA contenus dans des appareils SDR a été démontré dans le cadre du projet SDR-Makerspace avec la tâche SDR’s FPGA Partial reconfiguration. Ce projet est mené par le REDS en collaboration avec la Libre Space Foundation et il est…

Read More

Adding Build and Version Control Information in FPGA Bitstream

When handling FPGA bitstreams it would be nice to have a way to extract build and version information from them, especially when working with hardware-software designs. After generating a few different versions of a bitstream for a project it can be easy to lose track, especially when the design changes are not just incremental but alternative, e.g., to compare performance between possible implementations. In this post we will look at how to add build and version information to an FPGA…

Read More

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

Read More

Running Vivado in the Cloud

Vivado Vivado is one of our main tools when working with FPGAs. However when implementing for big FPGAs such as Kintex/Virtex Ultrascale devices, the processing can take forever when running with a high resource usage. The goal of this article is to show a way to tackle this problem and generate more bitstreams faster. By launching Vivado multiple times in the Cloud on instances of our choice (need 128 CPUs and 2TB of RAM, go ahead, just kidding, but this…

Read More
Find Us

Route de Cheseaux 1
CP 521
1401 Yverdon-les-Bains

About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at http://www.reds.ch