HPC

Exploring Intel(R) Core(TM) Ultra 7 155H

It is summer, the semester is over, and with many colleagues and students on holiday, there is finally a little time for experimenting. After years of impeccable service, I’ve recently updated my laptop, a Yoga 910-13IKB, to a new Yoga Slim 7i Gen 9 (14″ Intel). With this new laptop comes a new CPU: Intel(R) Core(TM) Ultra 7 155H. Considering this is the first time I’ve my hands on an heterogeneous CPU from Intel (working mostly on embedded big.LITTLE is…

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Exploring GNU Radio performance in 2020

It was 2018 when I first wrote a post about bench-marking in GNU Radio. This post will expand on that, focusing on one technology I am experimenting with (eBPF) and a bit hack. This year I taught a class on High Performance Coding and one of the chapters introduces some bit hacks. Reading the excellent material from MIT 6.172 Performance Engineering of Software Systems, I stumbled upon the modular addition bit hack implementation. Considering that what I did in the…

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Using the mSGDMA IP : an introduction

Hardware accelerated computations is a rising trend today. More and more, we are moving towards heterogeneous systems where a CPU and one or more hardware accelerators collaborate together to speedup computationally intensive tasks. FPGAs, with their reconfiguration capabilities, are very good candidates towards hardware acceleration. One very important part in this field is data transfers between a CPU and a hardware accelerator, as they are a critical in such a high performance environment. On FPGAs, though, how does data transfer…

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Link with the parallel version of libstdc++ and take advantage of your multi-core processor “for free”

Going from a single threaded program to a parallel version is often a major pain, this is however often needed to take full advantage of modern multi-core processors. Having to work with threads, locks, and shared data structures is often difficult due to the non deterministic behavior of the scheduler and the difficulty in debugging the complex problems that can happen with multi-threading. It should be noted that several algorithms in the C++ library already have a parallel implementation. If…

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About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at http://www.reds.ch