Socfpga

Socfpga, Tutorial

The ZynqUltraScale+ is a powerful SoC platform combining multi-core ARM64 CPUs and FPGA technology. There are plenty of projects that can take advantage of running a Linux kernel on the ARM64 processor and sometimes they require some degree of kernel hacking. In this post we will setup a build environment to modify the Linux kernel, compile it, and run it rapidly on a ZCU106 development board. For this we want the following : Be able to modify and compile the…

An ARM single board computer as PCIe card !?! (part 1)

June 5, 2023

In this blog post series I will show how we can use an ARM single board computer (SBC) as a PCIe card (PCIe endpoint). At REDS when developing PCIe based devices we usually rely on FPGAs, for example to develop FPGA PCIe accelerators. These are often based on existing PCIe cards from AMD (Xilinx) and Intel (Altera). For example the Xilinx Alveo series or Zynq based development boards. To develop accelerators such cards are fine and the development boards allow…

Adding Build and Version Control Information in FPGA Bitstream

June 2, 2020

One Comment

When handling FPGA bitstreams it would be nice to have a way to extract build and version information from them, especially when working with hardware-software designs. After generating a few different versions of a bitstream for a project it can be easy to lose track, especially when the design changes are not just incremental but alternative, e.g., to compare performance between possible implementations. In this post we will look at how to add build and version information to an FPGA…

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

May 20, 2020

17 Comments

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

A note on using the FPGA-to-SDRAM bus

May 13, 2019

Sydney Hauke

On Alter-Intel SoCs, there exist a bus connecting directly the FPGA fabric and the SDRAM called FPGA-to-SDRAM. This bus is not shared with any other peripheral and enables high-throughput data transfers between the FPGA and the SDRAM. Typically, you might want to use it for DMA transfers. By default, this bus might not be enabled and prevents anyone from attempting a single transfer on it. If your FPGA design interfaces with this bus, you might need to enable the bus’…

Using the mSGDMA IP : an introduction

May 13, 2019

Sydney Hauke

HPC, Socfpga

8 Comments

Hardware accelerated computations is a rising trend today. More and more, we are moving towards heterogeneous systems where a CPU and one or more hardware accelerators collaborate together to speedup computationally intensive tasks. FPGAs, with their reconfiguration capabilities, are very good candidates towards hardware acceleration. One very important part in this field is data transfers between a CPU and a hardware accelerator, as they are a critical in such a high performance environment. On FPGAs, though, how does data transfer…

Configuring the Cyclone V FPGA from a SD card

April 15, 2019

Damien Perrelet

Sometimes it is handy to have the CPU program the FPGA using a file stored on an SD card. This post shows you how this can be quickly done with Quartus and a Cyclone V-based board. Using Quartus Prime, convert the generated .sof file into .rbf without compression (menu: Convert programming files). Next, place the .rbf file thus created on the FAT32 partition of the SD card. U-Boot requires a boot script (u-boot.scr) that can be generated from a regular…

A quick note on some Arria 10 intricacies

February 22, 2019

Xavier Ruppen

3 Comments

A previous article on this blog, “Everything mainline from the ground up”, shows how to build mainline U-boot and Linux for Altera socfpgas. While the Cyclone V and the Stratix 10 are widely used and well supported, much cannot be said about the Arria 10. The Arria 10’s bitstream is separated in two parts: the so-called “peripheral” and “core” bitstreams (the A10 Reference Manual gives more information about this). While a single .sof file may contain both the peripheral and the…

Arria 10: adding support for the Reflex CES R329 board in Linux

February 21, 2019

Xavier Ruppen