A previous article on this blog, “Everything mainline from the ground up”, shows how to build mainline U-boot and Linux for Altera socfpgas. While the Cyclone V and the Stratix 10 are widely used and well supported, much cannot be said about the Arria 10.

The Arria 10’s bitstream is separated in two parts: the so-called “peripheral” and “core” bitstreams (the A10 Reference Manual gives more information about this). While a single .sof file may contain both the peripheral and the core sections, it is possible to separate it in two files from Quartus tools. The peripheral section, which is lighter, can be programmed first and the core section, which contains the heavier user logic, can be programmed later on, whenever one feels like it, effectively speeding up the boot process. Exploring the single-file version with your favorite hex editor (xxd) reveals that it really is merely a concatenation of both files with (nearly) no extra information.

So what’s the purpose of all of this? Some A10 peripherals may only be accessed after that the peripheral region has been loaded. For example, UART0, which is in the “Shared IO” region [1], and specifically the DDR controller are one of those peripherals. The consequence of this is that the SPL, which is executed from OCRAM, will not be able to relocate U-boot to the DDR and will crash before U-boot will even start executing. Note that this can be circumvented when the FPGA is programmed by any other mean, such as by using a JTAG probe (Blaster) or an EPCQ memory that programs the FPGA before running any HPS code.

On a side note, if you want to be able to program the FPGA from the HPS, it is required that the MSEL pins be correctly wired on the board. According to Intel’s documentation, the MSEL pins dictacte how the FPGA controller programs the FPGA logic. Depending on its configuration, it will be impossible to load any bitstream from the HPS. This was the case on an early version of the Reflex CES SoM which had them hardwired. A quick hardware mod was needed to allow programmation from the ARM processor.

While I am unsure about the current state of the A10’s development [2], it seems that mainline U-boot misses a way to program the FPGA while booting. However, this feature may be found in the maintainer’s custodian repository on the arria10_sdmmc branch, along other patches which may also be of importance. Be aware that this branch is not meant to be stable, may be rebased or even deleted at any time.

Using this branch, the u-boot-with-spl.sfp embeds a copy of the whole bitstream (read: periph + core) that is reprogrammed by the SPL before U-boot relocates itself into DDR and successfully runs from there. An .its file [3] tells the build system how to integrate the bitstream into the binary.

[1] As opposed to UART0, UART1 is in the “Dedicated IO” region and is available without any configuration. While the original Altera A10 socdk uses UART1, the A10 SoM by Reflex CES uses UART0 which may catch some developpers off guard.
[2] I recommend watching this excellent talk given by Marek Vasut at the Embedded Recipes 2018, “SoC+FPGA support in 2018”
[3] board/altera/arria10-socdk/fit_spl_fpga.its