REDS blog – Page 2 – REDS Institute, HEIG-VD

eclipse for nRF5 SDK installation guide

February 3, 2022

Introduction nRF5 SDK allows the development of software for the nRF51 and nRF52 SoCs. Nordic Semiconductor promotes the use of the nRF Connect SDK, but I found it complex to use because it doesn’t allow bare metal (it works with the RTOS Zephyr Project) and force you to use new tools like DeviceTree and CMake that I’m not proficient with. Nordic Semiconductor offers a free license to SEGGER Embedded Studio for development with nRF chips, but if you are like…

eclipse for nRF5 SDK using example

February 3, 2022

Nicolas Brunner

Tutorial

No Comments

Introduction In the previous article, we have learnt how to install the IDE. We will now use an example provided by the nRF5 SDK. We should be able to directly build the example found in the SDK, but I don’t like this method because we often need to make some changes and I like to keep the SDK in a pristine state. In this post, we will use the blinky example for the nRF52840DK (pca10056) found in nRF5 SDK 17.1.0.…

Accessing the RAM of a QEMU Emulated System from another Process

February 4, 2021

Rick Wertenbroek

Tutorial, Virtualization

2 Comments

Sometimes it may be of interest to expose the RAM of a hardware platform emulated in QEMU to an outside process, e.g., for monitoring, testing, or co-simulation. The QEMU monitor allows to inspect the memory but is not necessarily the most practical tool when you need to access it from another process, e.g., a C program or an external simulator, maybe Questasim simulating a device written in SystemVerilog. In this post I will show how to make the memory of…

Présentation des travaux de Bachelor de nos étudiants

September 29, 2020

Mathilde Chammartin

Uncategorized

No Comments

Durant le mois de septembre, nos étudiants ont présenté leurs travaux de Bachelor sous la direction de leurs professeurs respectifs. Nous leur souhaitons à tous plein succès pour leur avenir ! Professeur Alberto Dassatti Carpita Edoardo – “Amélioration des performances du module GRIDEYE” Eduardo a évalué et profilé en profondeur le traitement effectué sur un module commercial exécutant Linux sur ARM. Il a pu identifier quelques problèmes et proposer des solutions conduisant à une réduction de la charge des processeurs…

A guide to compile and install a Xenomai-patched kernel

September 16, 2020

Lucas Elisei

Tutorial

5 Comments

This tutorial will present how to compile and install a Xenomai-patched Linux kernel. Moreover, we will build Debian packages to ease the installation process. At the time of writing, the most recent stable version of Xenomai is 3.1 and the latest supported Linux kernel version is 4.19.89. However, these instructions should be valid for past and future versions. All the instructions have been executed on a machine running Ubuntu 20.04. Pre-requisites Install the following required packages: Download required files From…

La reconfiguration partielle sur FPGA pour des applications dans les appareils de radio définie par logiciel (SDR)

June 30, 2020

Sara Grassi

SDR

No Comments

L’une des spécialités de l’institut REDS est le développement de systèmes reconfigurables à haute performance, et l’une de ses activités principales est la radio définie par logiciel – Software Defined Radio (SDR). La faisabilité de la reconfiguration partielle sur des circuits FPGA contenus dans des appareils SDR a été démontré dans le cadre du projet SDR-Makerspace avec la tâche SDR’s FPGA Partial reconfiguration. Ce projet est mené par le REDS en collaboration avec la Libre Space Foundation et il est…

Exploring GNU Radio performance in 2020

June 29, 2020

Alberto Dassatti

HPC, SDR

No Comments

It was 2018 when I first wrote a post about bench-marking in GNU Radio. This post will expand on that, focusing on one technology I am experimenting with (eBPF) and a bit hack. This year I taught a class on High Performance Coding and one of the chapters introduces some bit hacks. Reading the excellent material from MIT 6.172 Performance Engineering of Software Systems, I stumbled upon the modular addition bit hack implementation. Considering that what I did in the…

Adding Build and Version Control Information in FPGA Bitstream

June 2, 2020

Rick Wertenbroek

Socfpga

One Comment

When handling FPGA bitstreams it would be nice to have a way to extract build and version information from them, especially when working with hardware-software designs. After generating a few different versions of a bitstream for a project it can be easy to lose track, especially when the design changes are not just incremental but alternative, e.g., to compare performance between possible implementations. In this post we will look at how to add build and version information to an FPGA…

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

May 20, 2020

Rick Wertenbroek

Socfpga

17 Comments

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

Smart Object Oriented (SOO) Technology

March 30, 2020

Daniel Rossier

Virtualization

No Comments

Introduction Smart Object Oriented (SOO) technology is the result of many years of research and development in the field of embedded systems including hardware and software topics such as ARM microcontrollers, System-on-Module integration, operating systems and software virtualization. The SOO framework has been released publicly on Gitlab in March 2020 under the GPLv2 Licence. Additional discussions and technical hints are also available in the dedicated forum. In early 2014, Prof. Daniel Rossier introduced the notion of Smart Object and the…