REDS blog – Page 2 – REDS Institute, HEIG-VD

Exploring GNU Radio performance in 2020

June 29, 2020

It was 2018 when I first wrote a post about bench-marking in GNU Radio. This post will expand on that, focusing on one technology I am experimenting with (eBPF) and a bit hack. This year I taught a class on High Performance Coding and one of the chapters introduces some bit hacks. Reading the excellent material from MIT 6.172 Performance Engineering of Software Systems, I stumbled upon the modular addition bit hack implementation. Considering that what I did in the…

Adding Build and Version Control Information in FPGA Bitstream

June 2, 2020

Rick Wertenbroek

Socfpga

One Comment

When handling FPGA bitstreams it would be nice to have a way to extract build and version information from them, especially when working with hardware-software designs. After generating a few different versions of a bitstream for a project it can be easy to lose track, especially when the design changes are not just incremental but alternative, e.g., to compare performance between possible implementations. In this post we will look at how to add build and version information to an FPGA…

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

May 20, 2020

Rick Wertenbroek

Socfpga

17 Comments

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

Smart Object Oriented (SOO) Technology

March 30, 2020

Daniel Rossier

Virtualization

No Comments

Introduction Smart Object Oriented (SOO) technology is the result of many years of research and development in the field of embedded systems including hardware and software topics such as ARM microcontrollers, System-on-Module integration, operating systems and software virtualization. The SOO framework has been released publicly on Gitlab in March 2020 under the GPLv2 Licence. Additional discussions and technical hints are also available in the dedicated forum. In early 2014, Prof. Daniel Rossier introduced the notion of Smart Object and the…

Retrospective on the SDR Makerspace conference

December 17, 2019

Sydney Hauke

Uncategorized

No Comments

On the 28th and 29th of November, the REDS institute of the HEIG-VD organized its very first international conference at the Swiss Aéropôle of Payerne on the topic of Software Defined Radio, driven by the SDR Makerspace initiative. Needless to say, the conference was overall a success. I have met motivated and enthusiastic attendees, all gathering around the exciting topic of Software Defined Radios. Industrialists, academicians, experts, hobbyists, and even students were present. As I said, the SDR Makerspace initiative…

SDR Makerspace Conference

October 3, 2019

Roberto Rigamonti

Uncategorized

No Comments

28-29 November 2019, Swiss Aeropole / Payerne (CH) The REDS institute of the Haute École d’Ingénierie et de Gestion of the Vaud canton (HEIG-VD), specialized in the development of high-performance reconfigurable systems, is organizing a conference on Software Defined Radios (SDRs) in the context of SDR Makerspace, a European Space Agency (ESA)-sponsored project. These “software radios” are transceivers that take advantage of the flexibility of software to attain unsurpassed performances in terms of robustness and adaptability, and this turns out…

A note on using the FPGA-to-SDRAM bus

May 13, 2019

Sydney Hauke

Socfpga

No Comments

On Alter-Intel SoCs, there exist a bus connecting directly the FPGA fabric and the SDRAM called FPGA-to-SDRAM. This bus is not shared with any other peripheral and enables high-throughput data transfers between the FPGA and the SDRAM. Typically, you might want to use it for DMA transfers. By default, this bus might not be enabled and prevents anyone from attempting a single transfer on it. If your FPGA design interfaces with this bus, you might need to enable the bus’…

Using the mSGDMA IP : an introduction

May 13, 2019

Sydney Hauke

HPC, Socfpga

8 Comments

Hardware accelerated computations is a rising trend today. More and more, we are moving towards heterogeneous systems where a CPU and one or more hardware accelerators collaborate together to speedup computationally intensive tasks. FPGAs, with their reconfiguration capabilities, are very good candidates towards hardware acceleration. One very important part in this field is data transfers between a CPU and a hardware accelerator, as they are a critical in such a high performance environment. On FPGAs, though, how does data transfer…

Configuring the Cyclone V FPGA from a SD card

April 15, 2019

Damien Perrelet

Socfpga

No Comments

Sometimes it is handy to have the CPU program the FPGA using a file stored on an SD card. This post shows you how this can be quickly done with Quartus and a Cyclone V-based board. Using Quartus Prime, convert the generated .sof file into .rbf without compression (menu: Convert programming files). Next, place the .rbf file thus created on the FAT32 partition of the SD card. U-Boot requires a boot script (u-boot.scr) that can be generated from a regular…

A quick note on some Arria 10 intricacies

February 22, 2019

Xavier Ruppen

Socfpga

3 Comments

A previous article on this blog, “Everything mainline from the ground up”, shows how to build mainline U-boot and Linux for Altera socfpgas. While the Cyclone V and the Stratix 10 are widely used and well supported, much cannot be said about the Arria 10. The Arria 10’s bitstream is separated in two parts: the so-called “peripheral” and “core” bitstreams (the A10 Reference Manual gives more information about this). While a single .sof file may contain both the peripheral and the…