Accessing the RAM of a QEMU Emulated System from another Process

Sometimes it may be of interest to expose the RAM of a hardware platform emulated in QEMU to an outside process, e.g., for monitoring, testing, or co-simulation. The QEMU monitor allows to inspect the memory but is not necessarily the most practical tool when you need to access it from another process, e.g., a C program or an external simulator, maybe Questasim simulating a device written in SystemVerilog. In this post I will show how to make the memory of…

Read More

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

Read More

Running Questasim on any OS through Docker

Questasim When doing HDL simulation Questasim is one of our main tools. However it only runs on Windows and GNU/Linux. Although we  mostly use GNU/Linux machines Questasim is not compatible with all distributions. This mainly because of library version compatibility, albeit this being fixable, it is a pain to do (find out which library is the culprit and which version is needed). So creating a Docker image seems like a good solution. It provides a known fixed environment to Questasim…

Read More
Find Us

Route de Cheseaux 1
CP 521
1401 Yverdon-les-Bains

About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at