Vivado

Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim

Introduction This is a step-by-step guide to enable hardware (PL) – software (PS) Co-Simulation with QEMU and QuestaSim for a Vivado Zynq project running a Linux operating system and applications. Being able to simulate the interactions between the software running on the ARM processing system (PS) and the FPGA Programmable Logic (PL) allows for full-system simulation and can help development of drivers as well as embedded software that relies on the PL. Prequisites Linux-based operating system Vivado (this guide uses…

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Running Vivado in the Cloud

Vivado Vivado is one of our main tools when working with FPGAs. However when implementing for big FPGAs such as Kintex/Virtex Ultrascale devices, the processing can take forever when running with a high resource usage. The goal of this article is to show a way to tackle this problem and generate more bitstreams faster. By launching Vivado multiple times in the Cloud on instances of our choice (need 128 CPUs and 2TB of RAM, go ahead, just kidding, but this…

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About This Site

Technical articles related to the development work performed at the REDS institute, HEIG-VD (Switzerland).

The REDS institute is part of the High School of Engineering, Vaud. Its core skills involve board conception, firmware development and FPGA programming.

Find more at http://www.reds.ch