Xilinx – REDS blog

Tux by Iwan Gabovitch (gg3po) Licensed under GPLv2

Linux kernel hacking on ZynqUltraScale+ with Petalinux

September 4, 2023

The ZynqUltraScale+ is a powerful SoC platform combining multi-core ARM64 CPUs and FPGA technology. There are plenty of projects that can take advantage of running a Linux kernel on the ARM64 processor and sometimes they require some degree of kernel hacking. In this post we will setup a build environment to modify the Linux kernel, compile it, and run it rapidly on a ZCU106 development board. For this we want the following : Be able to modify and compile the…

Adding Build and Version Control Information in FPGA Bitstream

June 2, 2020

Rick Wertenbroek

Socfpga

2 Comments

When handling FPGA bitstreams it would be nice to have a way to extract build and version information from them, especially when working with hardware-software designs. After generating a few different versions of a bitstream for a project it can be easy to lose track, especially when the design changes are not just incremental but alternative, e.g., to compare performance between possible implementations. In this post we will look at how to add build and version information to an FPGA…

Running Vivado in the Cloud

September 20, 2018

Rick Wertenbroek

Cloud Computing

6 Comments

Vivado Vivado is one of our main tools when working with FPGAs. However when implementing for big FPGAs such as Kintex/Virtex Ultrascale devices, the processing can take forever when running with a high resource usage. The goal of this article is to show a way to tackle this problem and generate more bitstreams faster. By launching Vivado multiple times in the Cloud on instances of our choice (need 128 CPUs and 2TB of RAM, go ahead, just kidding, but this…